1. Field of the Invention
The present invention relates to a method of forming a floating gate in a flash memory device, and more particularly, to a method of forming a floating gate using SASTI (self aligned shallow trench isolation) in the flash memory device.
2. Background of the Related Art
In NAND data flash memory devices currently being developed, a gate oxide thinning problem has been solved using SASTI (self aligned shallow trench isolation). However, there is still a difficulty in controlling a moat generated due to the height of a first polysilicon film and EFH (effective field oxide height). Furthermore, a slope is generated in the ISO (ISOlation) etch process, i.e., in trench formation process. Accordingly, it has influence on the profile of a subsequent HDP (high density plasma) oxide film, which causes to generate the slope even in the profile of the HDP oxide film. This slope of the HDP oxide film causes a bridge problem by residue of the first polysilicon film in the floating gate etch process. In addition, in a conventional STI process using a pad nitride film, there are problems that the pad nitride film remains in a large pattern and stress is applied to the wafer.